Differential amplifiers are common building blocks in integrated circuits. FIG. 1 shows differential amplifier 100, having a configuration known as “current mirror, plus source-coupled pair.” As shown in FIG. 1, differential amplifier 100 receives input signals INPUT0 and INPUT1 on gate terminals 111 and 112 of NMOS input transistors 103 and 104, respectively. Typically, input signals INPUT0 and INPUT1 constitute a differential signal. The source terminals of NMOS transistors 103 and 104 are connected in common (“COMMON SOURCE”). In differential amplifier 100, PMOS “load” transistor 101, which has its drain and gate terminals connected in common, provides a bias voltage (“BIAS”), which is “mirrored” to the gate terminal of PMOS transistor 102. Differential amplifier 100 also includes an enable and bias circuit which includes NMOS transistor 105. The gate terminal of NMOS transistor 105 receives signal enable_bias, which is deasserted when disabling of differential amplifier 100 is desired. When enable_bias is active, NMOS transistor 105 serves as a constant current source or a nearly constant current source.
As seen in FIG. 1, only signal OUTPUT1 at output terminal 114 can move within a substantial range between the supply voltage and the ground reference. Hence, differential amplifier does not provide a symmetrical output. Typically, the current source provided by the current mirror (i.e., PMOS transistor 101) is set to half in differential amplifier 100. Little current gain in the output is therefore provided under this arrangement, resulting in poor power efficiency.
To provide symmetrical output signals, the prior art uses two copies of differential amplifier 100 connected in the manner shown in FIG. 2. In FIG. 2, differential amplifiers 201 and 202 each receive the differential voltage across input terminals 210 and 211, but in opposite polarities. The asymmetrical output terminals 212 and 213 of differential amplifiers 201 and 202 provide a symmetrical differential output signal.